This is demonstration content.
Write the hypothesis first
A useful hypothesis can be disproved by an observation. “DMA never started” is better than “the driver is broken” because it maps to register state, bus events, and interrupt flags.
Change one variable at a time
Changing cache settings, clocks, and task priorities together makes even success impossible to explain. Preserve the minimal reproduction, versions, inputs, and results.
Define the finish line
A passing patch is not the end. Add a regression test, explain the root cause, and document why the change does not introduce a new timing risk.